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To study the effect of reference plane roughness on transmission insertion loss, Wildriver Technology’s custom modeling platform (CMP), shown in Figure 2, was used as a case study. Wildriver Isola I-Tera® MT40 Custom Modeling Platform Case Study Because the Cannonball-Huray model assumes the ratio of A matte/A flat = 1, and N i = 14 spheres, the radius of a sphere ( r) can be determined by: The Cannonball-Huray model allows you to extract the right parameters using Rz roughness for core and prepreg sides of the foil. Equation 1 assumes Rz of the foil on each side of the dielectric (core or prepreg) is the same.įor conductor loss, we use Rz roughness numbers from copper suppliers’ data sheets and oxide/oxide alternative Rz roughness numbers from your favorite fab shop, then apply the Cannonball-Huray roughness model. H = thickness of core/prepreg Rz is surface roughness of copper Dk is as published in laminate supplier’s Dk/Df tables. Heuristic HLD modeling is a practical technique that is not guaranteed to be perfect, but is still adequate in finding a satisfactory solution sooner, rather than later.įor dielectric parameters, we choose dielectric constant (Dk) / dissipation factor (Df) at or near the Nyquist frequency of the baud rate, then apply effective Dk ( Dkeff) correction factor due to roughness, Equation 1. So how do you know this before you design your stackup and build your first prototype? Since we do not have any empirical data to go by, we can rely on a heuristic, high-level design (HLD) modeling method starting with published parameters found solely in manufacturer’s data sheets.
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Thus, if insertion loss is a concern, copper foil roughness of reference planes needs to be considered.įigure 1 An example cross-section stripline geometry from a stackup showing thin core laminate (top) with RTF bonded to prepreg and adjacent to a high-speed differential pair with smooth foil. By the nature of their stackup construction, a rougher copper reference plane could sometimes also end up adjacent to a signal layer as well. This is a popular method to increase component density on modern PCBs. If that adjacent high-speed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly ruin your day.Ī similar scenario could occur for high density interconnect (HDI) technology. Sometimes one of these planes, usually GND, acts as a reference plane to an adjacent signal layer as shown in Figure 1. Often thin core laminate power and ground (GND) planes will specify reverse-treated foils (RTF), which are rougher on the side that bonds to the prepreg. If your design is running at 56Gig pulse amplitude modulation level 4 (PAM-4), for example, you are probably looking at low loss dielectrics and low roughness copper for the signal traces.īut what is sometimes overlooked in the stackup, is the roughness of the reference planes. Part of the stackup design process includes signal integrity (SI) modeling for characteristic impedance and transmission loss. Similarly for PCBs, you need a stackup drawing and detailed fabrication notes. Like any construction project, you need a blueprint before you start building. Thus a PCB stackup definition became vital for consistent performance. There was no such thing as a PCB stackup and nobody worried about impedance or transmission line losses.īut over the years PCBs have evolved into multi-layer constructions with evermore attention being paid to impedance control and transmission line losses. The only important metric for copper was its purity and the roughness to improve peel strength. Early PCBs were only constructed with single or double-sided copper core laminates. If your product has circuitry that is transmission loss sensitive, then paying attention to conductor surface roughness is paramount.Ĭonductor surface roughness traditionally has been applied to copper foil to promote adhesion to the dielectric material. ĭesigning the right printed circuit board (PCB) stackup can make or break your product performance. This article is an edited version of White Paper, “Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness in Printed Circuit Board Stackups”.